JPS6233327Y2 - - Google Patents

Info

Publication number
JPS6233327Y2
JPS6233327Y2 JP9907982U JP9907982U JPS6233327Y2 JP S6233327 Y2 JPS6233327 Y2 JP S6233327Y2 JP 9907982 U JP9907982 U JP 9907982U JP 9907982 U JP9907982 U JP 9907982U JP S6233327 Y2 JPS6233327 Y2 JP S6233327Y2
Authority
JP
Japan
Prior art keywords
stem
glass
lead wire
external lead
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9907982U
Other languages
English (en)
Japanese (ja)
Other versions
JPS593550U (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9907982U priority Critical patent/JPS593550U/ja
Publication of JPS593550U publication Critical patent/JPS593550U/ja
Application granted granted Critical
Publication of JPS6233327Y2 publication Critical patent/JPS6233327Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/71Means for bonding not being attached to, or not being formed on, the surface to be connected
    • H01L24/72Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP9907982U 1982-06-30 1982-06-30 大電力半導体用ステム Granted JPS593550U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9907982U JPS593550U (ja) 1982-06-30 1982-06-30 大電力半導体用ステム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9907982U JPS593550U (ja) 1982-06-30 1982-06-30 大電力半導体用ステム

Publications (2)

Publication Number Publication Date
JPS593550U JPS593550U (ja) 1984-01-11
JPS6233327Y2 true JPS6233327Y2 (en]) 1987-08-26

Family

ID=30234955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9907982U Granted JPS593550U (ja) 1982-06-30 1982-06-30 大電力半導体用ステム

Country Status (1)

Country Link
JP (1) JPS593550U (en])

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH063050B2 (ja) * 1986-07-26 1994-01-12 株式会社マブチ 組立型構造物に使用されるフロア・パネル

Also Published As

Publication number Publication date
JPS593550U (ja) 1984-01-11

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